The speed or performance of an integrated circuit is greatly dependent on the smallest control electrode length or gate length of an insulated transistor that can be reliably realized. The magnitude of the control electrode length may be subject to technological boundary conditions which limit said length. In a dynamic random access memory (DRAM), both a memory cell region or cell array and a peripheral region have to be produced in a process sequence. The memory cell region comprises control electrode tracks or gate conductor tracks for field-effect selection transistors which are assigned to memory cells, and gaps between the control electrode tracks having a specific distance (on pitch). By contrast, the peripheral region comprises the driving logic and clock generation, etc. for the memory cells in the memory cell region and/or another logic and usually likewise field-effect transistors with control electrode tracks and gaps between the control electrode tracks. Since it is necessary to effect optimization to the memory cell region in particular with regard to the control electrode lithography, however, the minimum insulated line width of a control electrode track of a transistor in the peripheral region cannot be chosen freely. This has the effect that a dynamic random access memory or an embedded dynamic random access memory which comprises both a memory cell region and a peripheral region is at a disadvantage with regard to the performance of the peripheral region compared with a pure logic circuit in which the entire lithography can be concentrated on the smallest insulated control electrode track. However, since the demands with regard to the performance of memory components, such as e.g. dynamic random access memories (DRAMs), are also increasing, improvements which are suitable for production and improve the performance of the transistors in the peripheral region of memory components are desirable.
In the figures, reference symbols which differ only in respect of the first numeral designate identical or functionally identical constituent parts.
FIG. 2 shows a known method for producing a memory component, and in particular the method for patterning the control electrode plane for a DRAM. FIG. 2A shows a substrate 200, in which there are already situated parts, such as e.g. wells, etc., of the later memory components and insulations 202 which divide the substrate 200 into a memory cell region 204 and a peripheral region 206. A control electrode oxide layer 208 or a gate oxide layer is applied on the substrate 200. A layer stack comprising a polysilicon layer 210, which is usually n-doped, and a tungsten silicide (WSix) layer 212 for increasing the conductivity is applied on the control electrode oxide layer 208. A patterning layer 214 or a cap layer made of silicon nitride (SiN) is applied on the layer stack. The patterning layer 214 is very important for patterning in the memory cell region 204, and there in particular for the production of the bit line contacts, which are not discussed in any further detail. In contrast to a logic circuit which is not divided into memory cell region and peripheral region, however, attention shall be drawn explicitly to the need for said patterning layer, even if the latter is rather disturbing in the peripheral region of a memory component. A resist mask 216 applied on the patterning layer 214 is patterned by means of photolithography, in such a way that it has open regions 216a and closed regions 216b. As already mentioned above, in the memory cell region 204, optimization is effected to the dimension of the line width 218 of a control electrode track in the memory cell region 204. The minimum line width 220 of a closed region 216b of the resist mask 216 which is assigned to an insulated control electrode track in the peripheral region 206 is then defined by the illumination conditions and the material parameters of the resist mask 216.
FIG. 2B shows that the patterning layer 214 is etched selectively with respect to the tungsten silicide layer 212, and the resist mask 216 is removed. The patterning layer 214 has open regions 214a and closed regions 214b equivalent to the resist mask 216. The etching changes the line width 218 of the closed regions 214b in the memory cell region 204, which are assigned to the control electrode tracks in the memory cell region 204, to a line width 222 and the line width 220 of the closed regions 214b in the peripheral region 206, which are assigned to control electrode tracks in the peripheral region 206, to a line width 224, which is referred to as the etching deviation or the etching bias of the mask opening step for opening the mask in the patterning layer 214.
FIG. 2C shows control electrode tracks 226 or control electrode stacks (gate stacks) for driving individual memory cells in the memory cell region 204 and control electrode tracks 228 for driving peripheral elements in the peripheral region 206 after the structures of the patterning layer 214 have been transferred to the layer stack of the polysilicon layer 210 and the tungsten silicide layer 212. The patterned patterning layer 214 was used as a hard mask for patterning the polysilicon layer 210 and the tungsten silicide layer 212. This control electrode etching step is designed in such a way that it stops on the control electrode oxide layer 208. During this method, once again the line width 222 of a closed region 214b assigned to a control electrode track in the memory cell region 204 changes to an actual line width 230 of the control electrode track 226 for driving the individual memory cells in the memory cell region 204, and the line width 224 of a closed region 214b assigned to a control electrode track in the peripheral region 206 changes to an actual line width 232 of the control electrode track 228 for driving the peripheral elements. This change in the line width corresponds to the etching deviation of the control electrode etching step. The change in the line width from FIG. 2B to 2C is small, however, during this step. The thickness of the patterning layer 214 additionally changes during the transfer of the structures, said patterning layer being reduced to a thickness 234 in this case. This change in the thickness is identical for both the memory cell region 204 and the peripheral region 206 after the control electrode track etching, within the bounds of small fluctuations.
FIG. 3A shows the production of typical control electrode tracks of a pure logic circuit which does not comprise different regions, such as e.g. a memory cell region and a peripheral region. These control electrode tracks differ in several points from the control electrode tracks of a memory component, such as e.g. a DRAM. The layer structure of the control electrode tracks comprises, similarly to FIG. 1, a substrate 300, a control electrode oxide layer 308 applied on the substrate 308, and a polysilicon layer 310 applied on the control electrode oxide layer 308. The polysilicon of polysilicon layer 310 is undoped at this point in time in the method, in order later to be able to realize transistors having n- and p-doped control electrodes or gates. In comparison with the structure of a memory component as shown in FIG. 2, the layer structure shown in FIG. 3 does not have a tungsten silicide layer, since the low resistance of the control electrode tracks can later be achieved by means of saliciding. This is possible in particular because no patterning layer or cap layer made of silicon nitride is used, rather an oxide layer 336 is instead deposited on the polysilicon layer 310, which is later consumed during the method. In the logic circuit shown in FIG. 3, there is no memory cell region in which the smallest insulated track of a control electrode track determines the process window, and the resist and the exposure conditions can be optimized thereto. A resist layer 316 is applied on the oxide layer 336, which resist layer is already patterned and has open regions 316a and closed regions 316b, the closed regions 316b having line widths 338 and 340 assigned to control electrode tracks.
FIG. 3B shows the layer structure after the transfer of the structure of the resist layer 316 to the oxide layer 336 and after the removal of the resist layer 316. During this transfer, open regions 336a and closed regions 336b are produced in the control electrode oxide layer 336, the closed regions 336b having line widths 342 and 344 assigned to control electrode tracks.
Finally, FIG. 3C shows the layer structure after the transfer of the structure of the oxide layer 336 to the polysilicon layer 310. The line widths 342, 344 of closed regions 336b of the oxide layer 336 are transferred into actual line widths 346, 348 of the control electrode tracks 350 or control stacks. The remaining oxide layer 336 is thinned compared with the original oxide layer shown in FIG. 3A and is removed in later method steps before the saliciding.
FIG. 4 shows a method for reducing the line width and/or the line length of a control electrode track or a control stack of individual transistors in logic circuits additionally below the lithographically governed minima. The structure shown in FIG. 4A once again has a substrate 400, on which a control electrode oxide layer 408 and a polysilicon layer 410 are applied. The logic circuit is divided into a first region 404 and a second region 406 by insulators 402. There is applied on the polysilicon layer 410 a patterned oxide layer 436 having open regions 436a and closed regions 436b, the structure of which corresponds to the structure shown in FIG. 3B. The closed regions 436b produced in the structure of the oxide layer 436, which are assigned to control electrode tracks, have line widths 442 and 444.
In FIG. 4A, a resist mask 452 is applied on a part of the logic circuit. In order to reduce the line width 444 of a closed region 436b assigned to a control electrode track in FIG. 4A, an isotropic etching is carried out, e.g. in hydrofluoric acid (HF), as a result of which the patterned closed regions 436b of the oxide layer 436 which are not covered by the resist layer 452 are reduced laterally to a line width 445 and vertically to a thickness 447. This step is generally called pull-back. The resist mask 452 is stripped or removed in a next step, e.g. by incineration, and an oxide layer 436 having different local thicknesses remains, which is shown in FIG. 4B. The oxide layer 436 therefore does not form a uniform plane, which may lead to problems e.g. in later polishing methods. Such problems must be avoided in particular in the case of memory components, such as e.g. DRAM memory components. In the case of logic circuits, in contrast to memory components, this is unimportant, however, since the oxide layer 436 has already fulfilled its function and can be removed. In the case of logic circuits, the isotropic etching step may, of course, also be carried out without a resist layer 452, and closed regions 436b assigned to control electrode tracks may simultaneously be diminished.
Finally, FIG. 4C shows the transfer of the structure of the oxide layer 436 to the polysilicon layer 410 in order to form control electrode tracks 450 having actual line widths 446 and 448.
A further possibility for realizing cell regions and very narrow insulated control electrode tracks in the control electrode conductor plane consists in a double exposure. This can be applied in principle to memory components, but has the disadvantages of a high outlay and of overlay problems during the exposure of subsequent planes.
Therefore, one disadvantage in the prior art is that, during the production of control electrode tracks for memory components, although the line width of control electrode tracks assigned to memory cells in a memory cell region of a memory component can be optimized optically and in terms of magnitude, at the same time it is possible as a result only to effect a limited reduction of the extent, such as e.g. reduction of the line width, of the control electrode tracks assigned to peripheral elements in a peripheral region of memory components. This problem is due to the fact that peripheral regions of memory components are typically provided with logic circuits, such as e.g. a driving logic or a clock generation, which do not have periodic structures but rather structures that are far away from one another, such as e.g. control electrode tracks, which do not afford any optical support during the exposure of the structures whereby the resolution could be improved and the line width minimized.
A further disadvantage in the prior art is that in alternative methods for setting the extent, such as e.g. the line width of control electrode tracks, in different regions of an integrated circuit, the known methods have the effect that the thickness of a patterning layer, such as e.g. a silicon nitride layer, varies, which leads to problems during later required polishing of the structure of the memory component.